The present invention relates to an electrostatic discharge device of a semiconductor device, and more particularly, to an electrostatic discharge device which is suitable for a semiconductor device operating at a high speed.
In general, electrostatic discharge (ESD) indicates a phenomenon that, when objects insulated from each other come into contact with each other electrically, current momentarily flows due to a considerably large difference in the voltages of the objects.
If a high voltage by ESD current flows to a semiconductor device, an internal circuit of the semiconductor device is likely to be damaged. Therefore, in most semiconductor devices, in order to protect internal circuits, an ESD protection circuit is installed between an input/output pad and the internal circuits.
FIG. 1 illustrates a conventional electrostatic discharge circuit.
Referring to FIG. 1, in order to protect an internal circuit 150 when static electricity is applied to an input/output pad I/O, a main electrostatic discharge section 110, an input resistor 120, an auxiliary electrostatic discharge section 130, and an input buffer 140 are formed between the input/output pad I/O and the internal circuit 150.
The main electrostatic discharge section 110 includes a first main electrostatic discharge unit 112 which is formed between the input/output pad I/O and a power voltage (VCC) line and a second main electrostatic discharge unit 114 which is formed between the input/output pad I/O and a ground voltage (VSS) line. The main electrostatic discharge section 110 is mainly constituted by diode chains and discharges static electricity, which is applied to the input/output pad I/O, to the power voltage (VCC) line or the ground voltage (VSS) line.
The input resistor 120 adjusts an on/off ratio. Similarly to the main electrostatic discharge section 110, the auxiliary electrostatic discharge section 130 discharges static electricity to the power voltage (VCC) line or the ground voltage (VSS) line when the static electricity is applied. The auxiliary electrostatic discharge section 130 functions to prevent the input buffer 140 from being damaged when static electricity is abruptly applied.
The input buffer 140 is composed of a PMOS transistor 142 and an NMOS transistor 144. If excessive voltages are applied to the gates of these transistors 142 and 144, the gate oxide layers of the transistors 142 and 144 are likely to be damaged. In order to prevent this, the auxiliary electrostatic discharge section 130 is used.
The auxiliary electrostatic discharge section 130 includes a PMOS transistor 132 which is formed between the input/output pad I/O and the power voltage (VCC) line and an NMOS transistor 134 which is formed between the input/output pad I/O and the ground voltage (VSS) line.
In the electrostatic discharge circuit, in order for the input resistor 120 to properly perform its function, the input resistor 120 should have resistance over a predetermined level (usually 100Ω). Consequently, in a semiconductor device operating at a high speed over several GHz, RC (resistance-capacitance) delay increases due to the resistance of the input resistor 120 and the capacitance of the back-end transistors 132 and 134. For example, in the case where a semiconductor device operates at a speed over several GHz, the rising time of a signal has the level of approximately 10 ps. In this regard, when assuming that the input resistor 120 has resistance of approximately 100Ω and the auxiliary electrostatic discharge section 130 has capacitance of approximately 0.1 pF, RC signal delay of an approximately 10 ps level occurs, which is intolerable.
If the resistance of the input resistor 120 is decreased so as to reduce the RC signal delay, when static electricity is produced, the probability of the transistors 132 and 134 of the auxiliary electrostatic discharge section 130 or the transistors 142 and 144 of the input buffer 140 to be damaged increases. That is to say, in the case where the resistance of the input resistor 120 is decreased, since the amount of current flowing through the transistors 132 and 134 of the auxiliary electrostatic discharge section 130 is increased, the transistors 132 and 134 are likely to be damaged unless the size of the transistors 132 and 134 is sufficiently large. Also, as the amount of current discharged through the transistors 132 and 134 increase, a voltage drop occurring due to the current and its path resistance increase. Accordingly, the gate insulation layers of the transistors 142 and 144 of the input buffer 140 are likely to be damaged.
In order to cope with these problems, the sizes of the transistors 132 and 134 of the auxiliary electrostatic discharge section 130 should be increased to a sufficient level. However, in this case, as an increased area of a chip is used, it is difficult to accommodate the trend toward the high integration of a semiconductor device.
Thus, in order to appropriately conform to the high speed operation of a semiconductor device, an electrostatic discharge circuit having relatively superior characteristics for protecting the gate insulation layers of the transistors of the input buffer and capable of minimizing signal delay is desired.